1. Field of the Invention
This invention relates in general to the field of microelectronics, and more particularly to a technique for incorporating architectural features into a microprocessor architecture beyond those provided for by the microprocessor's instruction set architecture.
2. Description of the Related Art
Since microprocessors were fielded in the early 1970's, their use has grown exponentially. Originally employed in the scientific and technical fields, microprocessor use has gravitated from those specialty fields into commercial consumer fields that include products such as desktop and laptop computers, video game controllers, and a host of other common household and business devices.
Along with this explosive growth in use over the past 30 years, the art has experienced a corresponding technology pull that is characterized by an escalating demand for increased speed, expanded addressing capabilities, faster memory accesses, larger operand size, more operations (e.g., floating point, single-instruction multiple data (SIMD), conditional moves, etc.), and added specialty operations (e.g., multi-media operations). This technology pull has resulted in an incredible number of advances in the art which have been incorporated in microprocessor designs such as extensive pipelining, super-scalar architectures, cache structures, out-of-order processing, burst access, branch predication, and speculative execution. Quite frankly, a present day microprocessor is an amazingly complex and capable machine in comparison to its 30-year-old predecessors.
But unlike many other products, there is another very important factor that has constrained, and continues to constrain, the evolution of microprocessor architecture. This factor, legacy compatibility, moreover accounts for a great deal of complexity in a present day microprocessor. For market-driven reasons, many producers have opted to incorporate new architectural features into updated microprocessor designs, but at the same time in these newer products they choose to retain all of the capabilities that are required to insure compatibility with older, so-called legacy application programs.
Nowhere has this legacy compatibility burden been more noticeable than can be seen in the development history of x86-compatible microprocessors. It is well known that a present day virtual-mode, 32-/16-bit x86 microprocessor is still capable of executing 8-bit, real-mode, application programs which were produced during the 1980's. And those skilled in the art will also acknowledge that a significant amount of corresponding architectural “baggage” is carried along in the x86 architecture for the sole purpose of supporting compatibility with legacy applications and operating modes. Yet, while in the past developers have been able to incorporate newly developed architectural features into existing instruction set architectures, the means whereby use of these features is enabled-programmable instructions-are becoming scarce. More succinctly, there are no more “spare” instructions in certain instruction sets of interest that provide designers with a means to incorporate newer features into an existing architecture.
In the x86 instruction set architecture, for example, there are no undefined 1-byte opcode states that have not already been used. All 256 opcode states in the primary 1-byte x86 opcode map are taken up with existing instructions. As a result, x86 microprocessor designers must presently make a choice between providing new features and abandoning legacy compatibility. If new programmable features are to be provided, then they must be assigned to opcode states. And if spare opcode states do not remain in an existing instruction set architecture, then some of the existing opcode states must be redefined to provide for the new features. Thus, legacy compatibility is sacrificed in order to provide for new feature growth.
What is needed is a technique that allows new architectural features to be incorporated into an existing microprocessor instruction set architecture that has a completely populated opcode structure, where the technique retains legacy application compatibility.